Hardware Verification Using Symbolic State Transition Graphs

In this paper, a new approach for hardware verification using symbolic state transition graph (implemented in BDDs) is presented . We propose a novel idea, symbolic state transition graph (symbolic STG), which can represent FSM in terms of the relations between symbolic input variables, state variables, and output results rather than the ezact input-output bit patterns. Compared to the conventional STG methods, the symbolic STG is more concise, higher-level, fewer states and easier t o specify. Based on the transition relation method and an event-driven scheduling technique to compute the symbolic states, we propose two algorithms to verify the circvit implementation with respect to its symbolic STGs. The algorithms can be used to find out a necessary condition for the implementation to satisfy the specification, which can be used for the allocation of design errors.